1. Field of the Invention
This invention generally relates to interrupt signals in a computer system, and more specifically relates to a circuit and method for converting interrupt signals from level trigger mode to edge trigger mode.
2. Description of the Related Art
In computer systems of the prior art, interrupt request lines from peripherals to the CPU were level sensitive. The interrupt converter generally detected the end of the interrupt acknowledge cycle as the end of the interrupt cycle. After waiting the minimum inactive time needed by the interrupt request input, the CPU would be ready to detect another active interrupt request signal. However, some peripherals require interrupt service that extends beyond the occurrence of the interrupt acknowledge signal, and would still be asserting the original interrupt request signal when the CPU became ready to detect another interrupt request signal. For this reason, the CPU would generate another interrupt cycle to service the interrupt, even though the interrupt was already being serviced. The CPU thus wasted the execution time of an extraneous interrupt cycle. This problem was caused by using the end of the interrupt acknowledge cycle as the end of the interrupt cycle, since the original level trigger mode interrupt request signal could still be active at this time and could be interpreted by the CPU as a second interrupt.
Therefore, there existed a need to provide a circuit and method for converting the interrupt request signals in a computer system from level trigger mode to edge trigger mode without an extraneous interrupt cycle. The circuit would thus detect an interrupt only after an End of Interrupt command is active, rather than looking only at the end of the interrupt acknowledge cycle. In this manner, the extraneous interrupt cycle inherent in the designs of the prior art is avoided.